The present invention relates generally to integrated circuits, and in particular to DEAPROM memory-with low tunnel barrier interpoly insulators which require refresh.
Flash memories have become widely accepted in a variety of applications ranging from personal computers, to digital cameras and wireless phones. Both INTEL and AMD have separately each produced about one billion integrated circuit chips in this technology.
The original EEPROM or EARPROM and flash memory devices described by Toshiba in 1984 used the interpoly dielectric insulator for erase. (See generally, F. Masuoka et al. xe2x80x9cA new flash EEPROM cell using triple polysilicon technology,xe2x80x9d IEEE Int. Electron Devices Meeting, San Francisco, pp. 464-67, 1984; F. Masuoka et al., xe2x80x9c256 K flash EEPROM using triple polysilicon technology,xe2x80x9d IEEE Solid-State Circuits Conf., Philadelphia, pp. 168-169, 1985). Various combinations of silicon oxide and silicon nitride were tried. (See generally, S. Mori et al., xe2x80x9creliable CVD inter-poly dialectics for advanced EandEEPROM,xe2x80x9d Symp. On VLSI Technology, Kobe, Japan, pp. 16-17, 1985). However, the rough top surface of the polysilicon floating gate resulted in, poor quality interpoly oxides, sharp points, localized high electric fields, premature breakdown and reliability problems.
Widespread use of flash memories did not occur until the introduction of the ETOX cell by INTEL in 1988. (See generally, U.S. Pat. No. 4,780,424, xe2x80x9cProcess for fabricating electrically alterable floating gate memory devices,xe2x80x9d Oct. 25, 1988; B. Dipert and L. Hebert, xe2x80x9cFlash memory goes mainstream,xe2x80x9d IEEE Spectrum, pp. 48-51, October, 1993; R. D. Pashley and S. K. Lai, xe2x80x9cFlash memories, the best of two worlds,xe2x80x9d IEEE Spectrum, pp. 30-33, December 1989). This extremely simple cell and device structure resulted in high densities, high yield in production and low cost. This enabled the widespread use and application of flash memories anywhere a non-volatile memory function is required. However, in order to enable a reasonable write speed the ETOX cell uses channel hot electron injection, the erase operation which can be slower is achieved by Fowler-Nordhiem tunneling from the floating gate to the source. The large barriers to electron tunneling or hot electron injection presented by the silicon oxide-silicon interface, 3.2 eV, result in slow write and erase speeds even at very high electric fields. The combination of very high electric fields and damage by hot electron collisions in the oxide result in a number of operational problems like soft erase error, reliability problems of premature oxide breakdown and a limited number of cycles of write and erase.
Other approaches to resolve the above described problems include; the use of different floating gate materials, e.g. SiC, SiOC, GaN, and GaAIN, which exhibit a lower work function (see FIG. 1A), the use of structured surfaces which increase the localized electric fields (see FIG. 1B), and amorphous SiC gate insulators with larger electron affinity, "khgr", to increase the tunneling probability and reduce erase time (see FIG. 1C).
One example of the use of different floating gate (FIG. 1A) materials is provided in U.S. Pat. No. 5,801,401 by L. Forbes, entitled xe2x80x9cFLASH MEMORY WITH MICROCRYSTALLINE SILICON CARBIDE AS THE FLOATING GATE STRUCTURE.xe2x80x9d Another example is provided in U.S. Pat. No. 5,852,306 by L. Forbes, entitled xe2x80x9cFLASH MEMORY WITH NANOCRYSTALLINE SILICON FILM AS THE FLOATING GATE.xe2x80x9d Still further examples of this approach are provided in pending applications by L. Forbes and K. Ahn, entitled xe2x80x9cDYNAMIC RANDOM ACCESS MEMORY OPERATION OF A FLASH MEMORY DEVICE WITH CHARGE STORAGE ON A LOW ELECTRON AFFINITY GaN OR GaAIN FLOATING GATE,xe2x80x9d Ser. No. 08/908098, and xe2x80x9cVARIABLE ELECTRON AFFINITY DIAMOND-LIKE COMPOUNDS FOR GATES IN SILICON CMOS MEMORIES AND IMAGING DEVICES,xe2x80x9d Ser. No. 08/903452.
An example of the use of the structured surface approach (FIG. 1B) is provided in U.S. Pat. No. 5,981,350 by J. Geusic, L. Forbes, and K. Y. Ahn, entitled xe2x80x9cDRAM CELLS WITH A STRUCTURE SURFACE USING A SELF STRUCTURED MASK.xe2x80x9d Another example is provided in U.S. Pat. No. 6,025,627 by L. Forbes and J. Geusic, entitled xe2x80x9cATOMIC LAYER EXPITAXY GATE INSULATORS AND TEXTURED SURFACES FOR LOW VOLTAGE FLASH MEMORIES.xe2x80x9d
Finally, an example of the use of amorphous SiC gate insulators (FIG. 1C) is provided in U.S. patent application Ser. No. 08/903453 by L. Forbes and K. Ahn, entitled xe2x80x9cGATE INSULATOR FOR SILICON INTEGRATED CIRCUIT TECHNOLOGY BY THE CARBURIZATION OF SILICON.xe2x80x9d
Additionally, graded composition insulators to increase the tunneling probability and reduce erase time have been described by the same inventors. (See, L. Forbes and J. M. Eldridge, xe2x80x9cGRADED COMPOSITION GATE INSULATORS TO REDUCE TUNNELING BARRIERS IN FLASH MEMORY DEVICES,xe2x80x9d application Ser. No. 09/945514.
The authors of the present invention have also previously described the concept of a programmable read only memory which requires refresh or is volatile as a consequence of leakage currents though gate dielectrics with a low tunnel barrier between a floating gate and the silicon substrate/well, transistor source, drain, and body regions. (See generally, L. Forbes, J. Geusic and K. Ahn, xe2x80x9cDEAPROM (Dynamic Electrically Alterable Programmable Read Only Memory) UTILIZING INSULATING AND AMORPHOUS SILICON CARBIDE GATE INSULATOR,xe2x80x9d application Ser. No. 08/902,843). An application relating to leakage currents through an ultrathin gate oxide has also been provided. (See generally, L. Forbes, E. H. Cloud, J. E. Geusic, P. A. Farrar, K. Y. Ahn, and A. R. Reinberg; and D. J. McElroy, and L. C. Tran, xe2x80x9cDYNAMIC FLASH MEMORY CELLS WITH ULTRATHIN TUNNEL OXIDES,xe2x80x9d U.S. Pat. No. 6,249,460).
However, all of these approaches relate to increasing tunneling between the floating gate and the substrate such as is employed in a conventional ETOX device and do not involve tunneling between the control gate and floating gate through an inter-poly dielectric.
Therefore, there is a need in the art to provide improved DEAPROM cells which increase memory densities while avoiding the large barriers to electron tunneling or hot electron injection presented by the silicon oxide-silicon interface, 3.2 eV, which result in slow write and erase speeds even at very high electric fields. There is also a need to avoid the combination of very high electric fields and damage by hot electron collisions in the which oxide result in a number of operational problems like soft erase error, reliability problems of premature oxide breakdown and a limited number of cycles of write and erase. Further, when using an interpoly dielectric insulator erase approach, the above mentioned problems of having a rough top surface on the polysilicon floating gate which results in, poor quality interpoly oxides, sharp points, localized high electric fields, premature breakdown and reliability problems must be avoided.
The above mentioned problems with DEAPROM memories and other problems are addressed by the present invention and will be understood by reading and studying the following specification. Systems and methods are provided for DEAPROM memories with metal oxide and/or low tunnel barrier interpoly insulators which require refresh. That is, the present invention describes the use of an ultra-thin metal oxide inter-poly dielectric insulators between the control gate and the floating gate to create a memory cell which has a high current gain, and is easy to program by tunneling but which requires refresh. The low barrier tunnel insulator between the floating gate and control gates makes erase of the cell easy but results in the requirement for refresh. These devices act like DRAM""s and can be utilized as DRAM replacements. A coincident address is achieved by addressing both the control gate address lines (y-address) and source address lines (x-address).
In one embodiment of the present invention, the DEAPROM memory includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposing the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator having a tunnel barrier of less than 1.5 eV. The low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of NiO, Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, Y2O3, Gd2O3, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3. The floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator. And, the control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.
These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.